About the Role
Lead silicon design for an AI accelerator, guiding development from FPGA prototype through ASIC tapeout and bring-up. As a founding member of a small silicon team, you will set technical direction and collaborate with PCB, interconnect, software, and systems teams to deliver the accelerator.
What You'll Do
Develop and optimize FPGA prototypes, taking designs from specification to working hardware.
Design and review synthesizable RTL for the first ASIC, with a focus on clean microarchitecture.
Build and maintain lint, simulation, synthesis, timing, and verification flows for rapid iteration and tapeout readiness.
Make architecture decisions across compute datapaths, memory systems, on-chip interconnect, and control logic.
Drive design through tapeout, bring-up, and delivery milestones.
Help grow and mentor the silicon team.
What We're Looking For
At least 8 years of experience in digital design or silicon engineering, building RTL, FPGA prototypes, or ASICs.
Experience shipping synthesizable SystemVerilog or Verilog and taking FPGA designs through synthesis, place-and-route, and deployment to working hardware.
Strong digital design fundamentals, including pipelining, clocks, resets, latency, throughput, and microarchitecture.
Experience designing compute datapaths and memory systems with bandwidth and latency constraints in mind.
Familiarity with simulation, linting, synthesis, SDC constraints, timing closure, and CDC verification.
Experience automating hardware flows with Python, Tcl, Make, Nix, or similar tools.
Background in AI accelerators or low-level AI kernels. Tapeout, high-speed interface, formal verification, UVM, cocotb, firmware, or systems-level hardware validation experience is also valuable.
Compensation & Benefits
Salary range: $200,000 to $300,000 annually. Visa sponsorship is available.
Location
On-site, full-time in San Francisco, United States. This role is not remote or hybrid.